View ADUM1100BR-RL7_3329086.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. e a adum1100 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. i coupler digital isolator features high data rate: dc to 100 mbps (nrz) compatible with 3.3 v and 5.0 v operation/ level translation 125 c max operating temperature low power operation 5 v operation 1.0 ma max @ 1 mbps 4.5 ma max @ 25 mbps 16.8 ma max @ 100 mbps 3.3 v operation 0.4 ma max @ 1 mbps 3.5 ma max @ 25 mbps 7.1 ma max @ 50 mbps 8-lead soic package (lead-free version available) high common-mode transient immunity: >25 kv/ s safety and regulatory information ul recognized 2500 v rms for 1 minute per ul 1577 csa component acceptance notice no. 5a vde certificate of conformity din en 60747-5-2 (vde 0884 part 2): 2003?1 din en 60950 (vde 0805): 2001?2; en 60950: 2000 v iorm = 560 v peak applications digital fieldbus isolation opto-isolator replacement computer-peripheral interface microprocessor system interface general instrumentation and data acquisition applications general description the adum1100 is a digital isolator based on analog devices i coupler technology. combining high speed cmos and mono- lithic air core transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives such as optocoupler devices. configured as a pin compatible replacement for existing high speed optocouplers, the adum1100 supports data rates as high as 25 mbps and 100 mbps. the adum1100 operates with either voltage supply ranging from 3.0 v to 5.5 v, boasts a propagation delay of <18 ns and edge asymmetry of <2 ns, and is compatible with temperatures up to 125 c. it operates at very low power, less than 0.9 ma of quies cent current (sum of both sides), and a dynamic current of less than 160 a per mbps of data rate. unlike other optocoupler alter- natives, the adum1100 provides dc correctness with a patented refresh feature that continuously updates the output signal. the adum1100 is offered in three grades. the adum1100ar and adum1100br can operate up to a maximum temperature of 105 c and support data rates up to 25 mbps and 100 mbps, respectively. the adum1100ur can operate up to a maximum temperature of 125 c and supports data rates up to 100 mbps. functional block diagram wa tchdog e n c o d e d e c o d e update v dd1 v i (data in) v dd1 gnd 1 v dd2 gnd 2 v o (data out) gnd 2 adum1100 for principles of operation, see method of operation, dc correctness, and magnetic field immunity section.
rev. e e2e adum1100especifications electrical specifications, 5 v operation 1 parameter symbol min typ max unit test conditions dc specifications input supply current i dd1(q) 0.3 0.8 ma v i = 0 v or v dd1 output supply current i dd2(q) 0.01 0.06 ma v i = 0 v or v dd1 input supply current (25 mbps) i dd1(25) 2.2 3.5 ma 12.5 mhz logic signal frequency (see tpc 1) output supply current 2 (25 mbps) i dd2(25) 0.5 1.0 ma 12.5 mhz logic signal frequency (see tpc 2) input supply current (100 mbps) i dd1(100) 9.0 14 ma 50 mhz logic signal frequency, (see tpc 1) adum1100br/adum1100ur only output supply current 2 (100 mbps) i dd2(100) 2.0 2.8 ma 50 mhz logic signal frequency, (see tpc 2) adum1100br/adum1100ur only input current i i e10 +0.01 +10 a0 v in v dd1 logic high output voltage v oh v dd2 e 0.1 5.0 v i o = e20 a, v i = v ih v dd2 e 0.8 4.6 v i o = e4 ma, v i = v ih logic low output voltage v ol 0.0 0.1 v i o = 20 a, v i = v il 0.03 0.1 v i o = 400 a, v i = v il 0.3 0.8 v i o = 4 ma, v i = v il switching specifications for adum1100ar minimum pulse width 3 pw 40 ns c l = 15 pf, cmos signal levels maximum data rate 4 25 mbps c l = 15 pf, cmos signal levels for adum1100br/adum1100ur minimum pulse width 3 pw 6.7 10 ns c l = 15 pf, cmos signal levels maximum data rate 4 100 150 mbps c l = 15 pf, cmos signal levels for all grades propagation delay time t phl 10.5 18 ns c l = 15 pf, cmos signal levels to logic low output 5, 6 (see tpc 3) propagation delay time t plh 10.5 18 ns c l = 15 pf, cmos signal levels to logic high output 5, 6 (see tpc 3) pulse width distortion |t plh e t phl | 6 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change versus temperature 7 3 ps/ cc l = 15 pf, cmos signal levels propagation delay skew t psk1 8nsc l = 15 pf, cmos signal levels (equal temperature) 6, 8 propagation delay skew t psk2 6nsc l = 15 pf, cmos signal levels (equal temperature, supplies) 6, 8 output rise/fall time t r , t f 3nsc l = 15 pf, cmos signal levels common-mode transient immunity |cm l |, 25 35 kv/ sv i = 0 or v dd1 , v cm = 1000 v, at logic low/high output 9 |cm h |t ransient magnitude = 800 v input dynamic power c pd1 35 pf dissipation capacitance 10 output dynamic power c pd2 8pf dissipation capacitance 10 see notes on page 5. specifications subject to change without notice. (4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v. all min/max specifications apply over the entire recommended operation range, unless otherwise noted. all typical specifications are at t a = 25 c, v dd1 = v dd2 = 5 v.)
rev. e e3e adum1100 electrical specifications, 3.3 v operation 1 parameter symbol min typ max unit test conditions dc specifications input supply current i dd1(q) 0.1 0.3 ma v i = 0 v or v dd1 output supply current i dd2(q) 0.005 0.04 ma v i = 0 v or v dd1 input supply current (25 mbps) i dd1(25) 2.0 2.8 ma 12.5 mhz logic signal frequency (see tpc 1) output supply current 2 (25 mbps) i dd2(25) 0.3 0.7 ma 12.5 mhz logic signal frequency (see tpc 2) input supply current (50 mbps) i dd1(50) 4.0 6.0 ma 25 mhz logic signal frequency, (see tpc 1) adum1100br/adum1100ur only output supply current 2 (50 mbps) i dd2(50) 1.2 1.6 ma 25 mhz logic signal frequency, (see tpc 2) adum1100br/adum1100ur only input current i i e10 +0.01 +10 a0 v in v dd1 logic high output voltage v oh v dd2 e 0.1 3.3 v i o = e20 a, v i = v ih v dd2 e 0.5 3.0 v i o = e2.5 ma, v i = v ih logic low output voltage v ol 0.0 0.1 v i o = 20 a, v i = v il 0.04 0.1 v i o = 400 a, v i = v il 0.3 0.4 v i o = 2.5 ma, v i = v il switching specifications for adum1100ar minimum pulse width 3 pw 40 ns c l = 15 pf, cmos signal levels maximum data rate 4 25 mbps c l = 15 pf, cmos signal levels for adum1100br/adum1100ur minimum pulse width 3 pw 10 20 ns c l = 15 pf, cmos signal levels maximum data rate 4 50 100 mbps c l = 15 pf, cmos signal levels for all grades propagation delay time to t phl 14.5 28 ns c l = 15 pf, cmos signal levels logic low output 5, 6 (see tpc 4) propagation delay time to t plh 15.0 28 ns c l = 15 pf, cmos signal levels logic high output 5, 6 (see tpc 4) pulse width distortion |t plh e t phl | 6 pwd 0.5 3 ns c l = 15 pf, cmos signal levels change versus temperature 7 10 ps/ cc l = 15 pf, cmos signal levels propagation delay skew t psk1 15 ns c l = 15 pf, cmos signal levels (equal temperature) 6, 8 propagation delay skew t psk2 12 ns c l = 15 pf, cmos signal levels (equal temperature, supplies) 6, 8 output rise/fall time t r , t f 3nsc l = 15 pf, cmos signal levels common-mode transient immunity |cm l |, 25 35 kv/ sv i =0 or v dd1 , v cm = 1000 v, at logic low/high output 9 |cm h |t ransient magnitude = 800 v input dynamic power dissipation c pd1 47 pf capacitance 10 output dynamic power dissipation c pd2 14 pf capacitance 10 see notes on page 5. specifications subject to change without notice. ( 3.0 v v dd1 3.6 v, 3.0 v v dd2 3.6 v. all min/max specifications apply over the entire recommended operation range, unless otherwise noted. all typical specifications are at t a = 25 c, v dd1 = v dd2 = 3.3 v.)
rev. e adum1100 e4e parameter symbol min typ max unit test conditions dc specifications input supply current, quiescent i ddi(q) 5 v/3 v operation 0.3 0.8 ma 3 v/5 v operation 0.1 0.3 ma output supply current, quiescent i ddo(q) 5 v/3 v operation 0.005 0.04 ma 3 v/5 v operation 0.01 0.06 ma input supply current, 25 mbps i ddi(25) 5 v/3 v operation 2.2 3.5 ma 12.5 mhz logic signal frequency 3 v/5 v operation 2.0 2.8 ma 12.5 mhz logic signal frequency output supply current, 25 mbps i ddo(25) 5 v/3 v operation 0.3 0.7 ma 12.5 mhz logic signal frequency 3 v/5 v operation 0.5 1.0 ma 12.5 mhz logic signal frequency input supply current, 50 mbps i ddi(50) 5 v/3 v operation 4.5 7.0 ma 25 mhz logic signal frequency 3 v/5 v operation 4.0 6.0 ma 25 mhz logic signal frequency output supply current, 50 mbps i ddo(50) 5 v/3 v operation 1.2 1.6 ma 25 mhz logic signal frequency 3 v/5 v operation 1.0 1.5 ma 25 mhz logic signal frequency input currents i ia e10 +0.01 +10 a0 v ia , v ib , v ic , v id v dd1 or v dd2 logic high output voltage, v oh v dd2 e 0.1 3.3 v i o = e20 a, v i = v ih 5 v/3 v operation v dd2 e 0.5 3.0 v i o = e2.5 ma, v i = v ih logic low output voltage, v ol 0.0 0.1 v i o = 20 a, v i = v il 5 v/3 v operation 0.04 0.1 v i o = 400 a, v i = v il 0.3 0.4 v i o = 2.5 ma, v i = v il logic high output voltage, v oh v dd2 e 0.1 5.0 v i o = e20 a, v i = v ih 3 v/5 v operation v dd2 e 0.8 4.6 v i o = e4 ma, v i = v ih logic low output voltage, v ol 0.0 0.1 v i o = 20 a, v i = v il 3 v/5 v operation 0.03 0.1 v i o = 400 a, v i = v il 0.3 0.8 v i o = 4 ma, v i = v il switching specifications for adum1100ar minimum pulse width 3 pw 40 ns c l = 15 pf, cmos signal levels maximum data rate 4 25 mbps c l = 15 pf, cmos signal levels for adum1100br/adum1100ur minimum pulse width 3 pw 20 ns c l = 15 pf, cmos signal levels maximum data rate 4 50 mbps c l = 15 pf, cmos signal levels for all grades propagation delay time to logic t phl, t plh low/high output 5, 6 5 v/3 v operation (see tpc 5) 13 21 ns c l = 15 pf, cmos signal levels 3 v/5 v operation (see tpc 6) 16 26 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh e t phl | 6 pwd 5 v/3 v operation 0.5 2 ns c l = 15 pf, cmos signal levels 3 v/5 v operation 0.5 3 ns c l = 15 pf, cmos signal levels change versus temperature 5 v/3 v operation 3 ps/?c c l = 15 pf, cmos signal levels 3 v/5 v operation 10 ps/?c c l = 15 pf, cmos signal levels propagation delay skew t psk1 (equal temperature) 6, 8 5 v/3 v operation 12 ns c l = 15 pf, cmos signal levels 3 v/5 v operation 15 ns c l = 15 pf, cmos signal levels electrical specifications, mixed 5 v/3 v or 3 v/5 v operation 1 (5 v/3 v operation: 4.5 v v dd1 5.5 v, 3.0 v v dd2 3.6 v. 3 v/5 v operation: 3.0 v v dd1 3.6 v, 4.5 v v dd2 5.5 v. all min/max specifications apply over the entire recommended operation range, unless otherwise noted. all typical specifications are at t a = 25 c, v dd1 = 3.3 v, v dd2 = 5 v or v dd1 = 5 v, v dd2 = 3.3 v.)
rev. e e5e adum1100 parameter symbol min typ max unit test conditions switching specifications (continued) propagation delay skew t psk2 (equal temperature, supplies) 6, 8 5 v/3 v operation 9 ns c l = 15 pf, cmos signal levels 3 v/5 v operation 12 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r , t f 3nsc l = 15 pf, cmos signal levels common-mode transient immunity at logic low/high output 8 |cm l |, 25 35 kv/ sv i = 0 or v dd1 , v cm = 1000 v, |cm h |t ransient magnitude = 800 v input dynamic power dissipation capacitance 10 c pd1 5 v/3 v operation 35 pf 3 v/5 v operation 47 pf output dynamic power dissipation capacitance 10 c pd2 5 v/3 v operation 8 pf 3 v/5 v operation 14 pf n otes 1 all voltages are relative to their respective ground. 2 output supply current values are with no output load present. the supply current drawn at a given signal frequency when an outp ut load is present is given by i dd 2 (l ) = i dd 2 + v dd 2 f c l , where i dd 2 is the unloaded output supply current, f is the input signal frequency, and c l is the output load capacitance. 3 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 t phl is measured from the 50% level of the falling edge of the v i signal to the 50% level of the falling edge of the v o signal. t plh is measured from the 50% level of the rising edge of the v i signal to the 50% level of the rising edge of the v o signal. 6 since the input thresholds of the adum1100 are at voltages other than the 50% level of typical input signals, the measured prop agation delay and pulse width distortion may be affected by slow input rise/fall times. see the propagation delay-related parameters section and figures 3 to 7 for information on the impact of given input rise/fall times on these parameters. 7 pulse width distortion change versus temperature is the absolute value of the change in pulse width distortion for a 1 c change in operating temperature. 8 t psk1 is the magnitude of the worst-case difference in t phl and/or t plh that will be measured between units at the same operating temperature and output load within the recommended operating conditions. t psk2 is the m agnitude of the worst-case difference in t phl and/or t plh that will be measured between units at the same oper ating temperature, supply voltages, and output load within the recommended operating conditions. 9 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling edges. the transient magnitude is the range over which the common-mode is slewed. 10 the dynamic power dissipation capacitance is given by c pdi = ( i ddi (100) e i ddi ( q ) )/( v ddi f ), where i = 1 or 2 and f is the input signal frequency. the supply current consumptions at a given frequency and output load are calculated as i dd 1 = c pd 1 v dd 1 f + i dd 1( q ) ; i dd 2( l ) = ( c pd 2 + c l ) v dd 2 f + i dd 2( q ) , where c l is the output load capacitance. specifications subject to change without notice. package characteristics parameter symbol min typ max unit test conditions resistance (input-output) 1 r ieo 10 12 capacitance (input-output) 1 c ieo 1pff = 1 mhz input capacitance 2 c i 4.0 pf input ic junction-to-case jci 46 c/w thermocouple located at center thermal resistance underside of package output ic junction-to-case jco 41 c/w thermal resistance package power dissipation p pd 240 mw n otes 1 device considered a 2-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 2 input capacitance is measured at pin 2 (v i ).
rev. e adum1100 e6e insulation and safety-related specifications parameter symbol value unit conditions minimum external air gap (clearance) l(i01) 4.90 min mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 4.01 min mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.016 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) din en 60747-5-2 (vde 0884 part 2) insulation characteristics description symbol characteristic unit i nstallation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification adum1100ar and adum1100br 40/105/21 adum1100ur 40/125/21 pollution degree (din vde 0110, table i) 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input-to-output test voltage, method a v pr 672 v peak after environmental tests subgroup 1 v iorm 1.6 = v pr , t m = 10 sec, partial discharge < 5 pc v pr 896 v peak after input and/or output safety test subgroup 2/3 v iorm 1.2 = v pr , t m = 10 sec, partial discharge < 5 pc v pr 672 v peak highest allowable overvoltage (transient overvoltage, t ini = 60 sec) v tr 4000 v peak safety-limiting values (maximum value allowed in the event of a failure, see thermal derating curve, figure 1 case temperature t s 150 c input current i s, input 160 ma output current i s, output 170 ma insulation resistance at t s , v io = 500 v rs >10 9 this isolator is suitable for basic isolation only within the safety limit data. maintenance of the safety data shall be ensure d by means of protective circuits. the * marking on the package denotes din en 60747-5-2 approval for 560 v peak working voltage. regulatory information the adum1100 has been approved by the following organizations: ul csa vde recognized under 1577 approved under csa component certified according to component recognition program 1 acceptance notice no. 5a, c22.2 no. 1-98, din en 60747-5-2 (vde 0884 part 2): 2003e1 2 c22.2 no. 14-95, and c22.2 no. 950-95 din en 60950 (vde 0805): 2001e12; en60950: 2000 file e214100 file 205078 file 2471900-4880-0002 n otes 1 in accordance with ul 1577, each adum1100 is proof tested by applying an insulation test voltage 3000 v rms for 1 second (leakage detection current limit, i ieo 5 a). 2 in accordance with din en 60747-5-2, each adum1100 is proof tested by applying an insulation test voltage 1050 v peak for 1 second (partial discharge detection limit 5 pc). a * mark branded on the component designates din en 60747-5-2 approval.
rev. e adum1100 e7e case temperature ( c) 180 0 safety-limiting current (ma) 100 80 0 50 100 150 200 120 160 140 20 40 60 input current output current figure 1. thermal derating curve, dependence of safety-limiting values with case temperature per din en 60747-5-2 absolute maximum ratings 1 parameter symbol min max unit storage temperature t st e55 +150 c ambient operating t a e40 +125 c temperature supply voltages 2 v dd1 , v dd2 e0.5 +6.5 v input voltage 2 v i e0.5 v dd1 + 0.5 v output voltage 2 v o e0.5 v dd2 + 0.5 v average current, per pin 3 temperature 105 c e25 +25 ma temperature 125 c input current e7 +7 ma output current e20 +20 ma common-mode transients 4 e100 +100 kv/ s notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. ambient temperature = 25 c, unless otherwise noted. 2 all voltages are relative to their respective ground. 3 see figure 1 for information on maximum allowable current for various temperatures. 4 refers to common-mode transients across the insulation barrier. common-mode transients exceeding the absolute maximum rating may cause latch-up or permanent damage. recommended operating conditions parameter symbol min max unit operating temperature adum1100ar and adum1100br t a e40 +105 c adum1100ur t a e40 +125 c supply voltages 1 v dd1, v dd2 3.0 5.5 v logic high input voltage, 5 v operation 1, 2 (see tpcs 7 and 8) v ih 2.0 v dd1 v logic low input voltage, 5 v operation 1, 2 (see tpcs 7 and 8) v il 0.0 0.8 v logic high input voltage, 3.3 v operation 1, 2 (see tpcs 7 and 8) v ih 1.5 v dd1 v logic low input voltage, 3.3 v operation 1, 2 (see tpcs 7 and 8) v il 0.0 0.5 v input signal rise and fall times 1.0 ms notes 1 all voltages are relative to their respective ground. 2 input switching thresholds have 300 mv of hysteresis. see the method of operation, dc correctness, and magnetic field immunity section and figures 8 and 9 for information on immunity to external magnetic fields.
rev. e adum1100 e8e ordering guide temperature max data min pulse package model range rate (mbps) width (ns) package description option adum1100ar e40 c to +105 c2 54 0 8-lead soic r-8 adum1100ar-rl7 e40 c to +105 c2 54 0 8-lead soic, 1,000 piece reel r-8 adum1100arz * e40 c to +105 c2 54 0 8-lead soic r-8 adum1100arz-rl7 * e40 c to +105 c2 54 0 8-lead soic, 1,000 piece reel r-8 adum1100br e40 c to +105 c 100 10 8-lead soic r-8 ADUM1100BR-RL7 e40 c to +105 c 100 10 8-lead soic, 1,000 piece reel r-8 adum1100brz * e40 c to +105 c 100 10 8-lead soic r-8 adum1100brz-rl7 * e40 c to +105 c 100 10 8-lead soic, 1,000 piece reel r-8 adum1100ur e40 c to +125 c 100 10 8-lead soic r-8 adum1100ur-rl7 e40 c to +125 c 100 10 8-lead soic, 1,000 piece reel r-8 adum1100urz * e40 c to +125 c 100 10 8-lead soic r-8 adum1100urz-rl7 * e40 c to +125 c 100 10 8-lead soic, 1,000 piece reel r-8 adum1100eval evaluation board * z = lead free note: package branding is as follows: 8 1 ad1100u r yyww * xxxxxx adum1100ur, adum1100ur-rl7 8 1 ad1100b r yyww * xxxxxx adum1100br, ADUM1100BR-RL7 8 1 ad1100a r yyww * xxxxxx adum1100ar, adum1100ar-rl7 where: * = din en 60747-5-2 mark r= package designator (r denotes soic) yyww = date code xxxxxx = lot code pin configuration adum1100 top view (not to scale) 8 7 6 5 1 2 3 4 v dd1 1 v i v dd1 1 gnd 1 v dd2 gnd 2 2 v o gnd 2 2 notes 1 pin 1 and pin 3 are internally connected. either or both may be used for v dd1 . 2 pin 5 and pin 7 are internally connected. either or both may be used for gnd 2 . caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adum1100 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table i. truth table (positive logic) v i input v dd1 state v dd2 state v o output h powered powered h l powered powered l x unpowered powered h * x powered unpowered x * * v o returns to v i state within 1 s of power restoration.
rev. e adum1100 e9e da ta rate (mbps) 20 0 current (ma) 18 16 2 0 25 50 75 100 125 150 14 12 10 8 6 4 5v 3.3v tpc 1. typical input supply current vs. logic signal frequency for 5 v and 3.3 v operation da ta rate (mbps) 5 0 current (ma) 3 2 1 0 25 50 75 100 125 150 5v 3.3v 4 tpc 2. typical output supply current vs. logic signal frequency for 5 v and 3.3 v operation temperature ( c) 13 e50 propagation delay (ns) 11 9 05075 100 125 12 t phl e25 25 t plh 10 tpc 3. typical propagation delays vs. temperature, 5 v operation temperature ( c) 18 e50 propagation delay (ns) 14 13 12 e25 25 50 100 125 15 17 16 075 t phl t plh tpc 4. typical propagation delays vs. temperature, 3.3 v operation temperature ( c) 14 e50 propagation delay (ns) 11 10 9 e25 25 50 100 125 12 13 075 t phl t plh tpc 5. typical propagation delays vs. temperature, 5 v/3 v operation temperature ( c) 18 e50 e25 125 propagation delay (ns) 16 14 13 12 0255 075 100 t phl t plh 17 15 tpc 6. typical propagation delays vs. temperature, 3 v/5 v operation t ypical performance characteristics?
rev. e adum1100 e10e 1.7 3.0 1.3 1.2 1.1 3.5 4.0 4.5 5.0 5.5 1.4 1.6 1.5 e40 c +25 c +125 c input supply voltage, v dd1 (v) input threshold, v ith (v) tpc 7. typical input voltage switching threshold, low-to-high transition input supply voltage, v dd1 (v) 1.4 3.0 input threshold, v ith (v) 1.0 0.9 0.8 3.5 4.0 4.5 5.0 5.5 1.1 1.3 1.2 e40 c +25 c +125 c tpc 8. typical input voltage switching threshold, high-to-low transition lh v ith(hel) input (v i ) v ith(leh) v i hl t phl t' phl t plh t' plh output (v o ) 50% 50% figure 4. impact of input rise/fall time on propagation delay application information pc board layout the adum1100 digital isolator requires no external interface circuitry for the logic interfaces. a bypass capacitor is recom- mended at the input and output supply pins. the input bypass capacitor may most conveniently be connected between pins 3 and 4 (figure 2). alternatively, the bypass capacitor may be located between pins 1 and 4. the output bypass capacitor may be con- nected between pins 7 and 8 or pins 5 and 8. the capacitor value should be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. v dd1 v 1 (data) gnd 1 v dd2 v o (data out) gnd 2 (optional) figure 2. recommended printed circuit board layout input (v i ) output (v o ) t plh t phl 50% 50% figure 3. propagation delay parameters propagation delay-related parameters propagation delay time describes the length of time it takes for a logic signal to propagate through a component. propagation delay time to logic low output and propagation delay time to logic high output refer to the duration between an input signal transition and the respective output signal transition (figure 3). pulse width distortion is the maximum difference between t plh and t phl and provides an indication of how accurately the input signal?s timing is preserved in the component?s output signal. propagation delay skew is the difference between the minimum and maximum propagation delay values among multiple adum1100 compo- nents operated at the same operating temperature and having the same output load. depending on the input signal rise/fall time, the measured propa- gation delay based on the input 50% level can vary from the true propagation delay of the component (as measured from its input switching threshold). this is due to the fact that the input threshold, as is the case with commonly used optocouplers, is at a different voltage level than the 50% point of typical input signals. this propagation delay difference is given by lh plh plh r i ith l h hl phl phl f i ith h l tt tvvv tt tvvv =?= () ? () =?= () ? () ? () ? () '/.. '/.. 08 05 08 05 1 1 where: t plh , t phl = propagation delays as measured from the input 50% level. t plh , t phl = propagation delays as measured from the input switching thresholds. t r , t f = input 10% to 90% rise/fall time. v i =a mplitude of input signal (0 to v i levels assumed). v ith ( leh ) , v ith ( hel ) = input switching thresholds.
rev. e adum1100 e11e input rise time (10%e90%, ns) 4 1 propagation delay change, lh (ns) 2 0 36810 3 1 5v input signal 24579 3.3v input signal figure 5. typical propagation delay change due to input rise time variation (for v dd1 = 3.3 v and 5 v) input rise time (10%e90%, ns) 0 1 propagation delay change, hl (ns) e2 e4 36810 e1 e3 24579 3.3v input signal 5v input signal figure 6. typical propagation delay change due to input fall time variation (for v dd1 = 3.3 v and 5 v) the impact of the slower input edge rates can also affect the measured pulse width distortion as based on the input 50% level. this impact may either increase or decrease the apparent pulse width distortion depending on the relative magnitudes of t phl , t plh , and pwd. the case of interest here is the condition that leads to the largest increase in pulse width distortion. the change in this case is given by pwd lh hl ith l h ith h l rf pwd pwd tvvv v for t t t = = = () () == () () () ee /. e e , ee 08 1 where: pwd t t pwd t t plh phl plh phl = = e e this adjustment in pulse width distortion is plotted as a func- tion of input rise/fall time in figure 7. input rise/fall time (10%e90%, ns) 6 1 pulsewidth distortion adjustment, pwd (ns) 3 0 36810 5 1 5v input signal 24579 3.3v input signal 2 4 figure 7. typical pulse width distortion adjustment due to input rise/fall time variation (at v dd1 = 3.3 v and 5 v) method of operation, dc correctness, and magnetic field immunity referring to the functional block diagram, the two coils act as a pulse transformer. positive and negative logic transitions at the isolator input cause narrow (2 ns) pulses to be sent via the trans- former to the decoder. the decoder is bistable and therefore either set or reset by the pulses indicating input logic transitions. in the absence of logic transitions at the input for more than 2 s, a periodic update pulse of the appropriate polarity is sent to ensure dc correctness at the output. if the decoder receives none of these update pulses for more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a logic high state by the watchdog timer circuit. the limitation on the adum1100?s magnetic field immunity is set by the condition in which induced voltage in the transformer?s receiving coil is sufficiently large to either falsely set or reset the decoder. the analysis that follows defines the conditions under which this may occur. the adum1100?s 3.3 v operating condi- tion is examined because it represents the most susceptible mode of operation. the pulses at the transformer output are greater than 1.0 v in amplitude. the decoder has sensing thresholds at about 0.5 v, therefore establishing a 0.5 v margin in which induced voltages can be tolerated. the induced voltage induced across the receiving coil is given by vddt rn n n = () = e/ ;, ,.... , 2 12 where: = magnetic flux density (gauss). n = number of turns in receiving coil. r n = radius of n th turn in receiving coil (cm).
rev. e adum1100 e12e given the geometry of the receiving coil in the adum1100 and an imposed requirement that the induced voltage be at most 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 8. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k figure 8. maximum allowable external magnetic field for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and will not cause a faulty output transition. similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 v to 0.75 v?still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the adum1100 transformers. figure 9 expresses these allowable current m agnitudes as a function of frequency for selected distances. as can be seen, the adum1100 is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. for the 1 mhz example noted, one would have to place a current of 0.5 ka 5 mm away from the adum1100 to affect the component?s operation. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm figure 9. maximum allowable current for various current-to-adum1100 spacings note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility.
rev. e adum1100 e13e outline dimensions 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa
rev. e adum1100 e14e revision history location page 10/03?data sheet changed from rev. d to rev. e. changes to product name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to regulatory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to din en 60747-5-2 (vde 0884 part 2) insulation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 changes to recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6/03?data sheet changed from rev. c to rev. d. changed din en 60747-5-2 (vde 0884 part 2) insulation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4/03?data sheet changed from rev. b to rev. c. changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to patent note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to regulatory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to insulation characteristics section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 changes to package branding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 changes to method of operation, dc correctness, and magnetic field immunity section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 replaced figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1/03?data sheet changed from rev. a to rev. b. added adum1100ur grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changed adum1100ar/adum1100br to adum1100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 added electrical specifications, mixed 5 v/3 v or 3 v/5 v operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated regulatory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to vde 0884 insulation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 changes to package branding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 updated tpcs 3e8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 deleted i coupler in field bus networks section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 added a new figure 9 and related text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 11/02?data sheet changed from rev. 0 to rev. a. edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to regulatory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to vde 0884 insulation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 added revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
e15e
e16e c02462e0e10/03(e)

▲Up To Search▲

Price & Availability of ADUM1100BR-RL7

	To Download ADUM1100BR-RL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .